Quant jobs / UBS

APAC Algo Trading Low Latency C++ Developer

Develop very low-latency trading controls using C++ and FPGA technology. The role combines real-time risk checks with hardware integration and network-performance analysis.

What you’d work on

Our reading of the posting: what a new hire in this role would most likely spend their first months on.

Implement deterministic trading rules and risk checks.
Integrate C++ components with FPGA acceleration.
Build verification tools and investigate latency bottlenecks.
Optimise shared-memory and lock-free communication.

What they ask for

Required

Low-latency C++ or FPGA development
Modern C++ and Linux
Concurrency and shared memory
High-speed networking
Hardware toolchains

Preferred

Market microstructure and FIX or ITCH

Education: Degree in computing, electrical engineering or a related subject; level not specified.
Experience: At least 7 years in FPGA or low-latency C++ development.
Languages and tools: C++
Verilog
VHDL
Linux
Vivado
Quartus
Markets: multi-asset

How to prepare

Benchmark a C++ risk check with tail-latency measurements.
Implement and verify a lock-free message path.
Compare software and FPGA designs for a deterministic trading rule.

What to study

The HFT Quant Developer roadmap sets out the stages for this kind of role, with free resources for each.

Open the roadmap

Apply

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View the posting on UBS’s site ↗

SelfMadeQuant wrote this summary from the employer’s public posting, last checked 6 November 2026. SelfMadeQuant isn’t affiliated with UBS and doesn’t handle applications.